Multiplier is a basic building block of each and every DSP system. In fact, one can argue to such system is nothing else but set of multiply accumulate (MACC) operations. Therefore this project starts with multiplier design. There are multiple options available in the literature, designed with different objectives in mind. Some target small HW resource utilisation, whereas others focus on high speed and low latency.
Since multiplication will be truly ubiquitous operation throughout this project, minimising latency associated with it seems like the best idea. This will prevent extra delays building-up at each and every step of processing. Therefore Wallace Tree architecture was the primary choice. However said that, this decision might have a negative impact on resource utilisation. Therefore, Dadda Multiplier architecture will be implemented as a backup. Then, resource utilisation and latency of both approaches will be compared. Depending on the outcome, the final decision will be made.
For simplicity, only one data format will be used - one sign bit, one integer bit and sixteen bits for fractional part. In other words, s18 format was selected to represent data. As far as the author can say, this is a common choice for DSP systems. But this implies an output of each and every mutlipication will be in s36 format, assuming the worst case scenario. Therefore, additional scaling needs to be implemented to bound multiplication results to reasonable number of bits, preferably to 18. This will be done as part of multiplier implementation. Actual possibilities will be discussed later.